This invention relates to coated ceramic objects and more particularly to coated ceramic substrates useful for mounting integrated circuit chips.
Ceramics are widely used as substrates and containers for integrated circuit modules. While the utilization of ceramic substrates offers many advantages in the manufacture of integrated circuits, problems do exist. For example, a recent relatively serious problem is referred to as the soft error rate (SER) of the integrated circuit. While minimum SER levels are tolerated, excessive levels are unacceptable.
There are two general ways in which integrated circuit chips are mounted upon or in a carrying structure, i.e., substrate. That is, the integrated circuit chip can be faced down toward the carrying substrate or can be faced away from the carrying substrate but, perhaps, towards other ceramic materials. The first technique involving contacts down is known in the art as face down or flip chip bonding. The second is generally called in the art backside bonding. The present invention is primarily described in terms of face down or flip chip bonding, but may be equally applicable to backside bonded chips.
In face down or flip chip bonding, the SER problem stems, in part, from alpha-particles being emitted from atomic radioactive impurities in the composition of the ceramic substrate, upon which the integrated circuit chips are mounted. These alpha-particles cross over the narrow gap between the substrate and the chip and collide with the chip causing an electronic noise burst. This electronic noise burst may be detected by part of the integrated circuit chip and may be mistaken for a logic signal, thereby leading to an error, which is called a "soft-fail". Further, similar errors may occur in electronic memories where radiation may flip information bits, e.g. a zero may be changed to a one.
One prior art procedure, which has been followed in an attempt to reduce soft error rates, involves squirting, under high pressure, a polymer believed to be a silicon containing polymer, between the already mounted chip and the nearby ceramic surfaces and then curing the inserted polymer. The resulting cured polymer layer is adequate to absorb the alpha-particles emitted by the ceramic, thus preventing them from reaching the integrated circuit. While this prior art procedure has been relatively successful in reducing soft error rates, it is an expensive operation.
Another problem associated with the utilization of ceramic substrates for mounting integrated circuits relates to the porosity and surface roughness of the ceramic carrying structure. It is known that the results obtained by depositing metal on the ceramic substrate is greatly influenced by the roughness of the ceramic surface. For example, excessive pitting on the ceramic surface results in gaps between metal line circuitry and the ceramic base, as well as, metal lines which break when they dip into the pitholes. Results of this kind will generally cause circuitry failures and thus samples exhibiting excessive flaws of this nature are usually discarded. Although ceramics with increased surface smoothness are commercially available, they are generally relatively expensive and thus may not present a commercially acceptable solution to the problem.
A method for reducing the porosity and surface roughness of ceramic substrates is disclosed in U.S. Pat. No. 4,230,773. This patent discloses a process wherein the application of sequential layers of coating reduces the surface roughness of a ceramic in a gradual manner. The manner generally includes applying a liquid coating containing at least one nonpolymeric silicon compound, such as a liquid organosilicon, and/or ethylenically unsaturated organosilicon compound, to at least one surface of the ceramic substrate. The coated substrate is then dried and subjected to elevated temperatures in order to convert the silicon compound to silicon oxides, which provides a smooth surface to the ceramic.
Thus, while the method of U.S. Pat. No. 4,230,773 may provide one solution to the surface roughness of the ceramic substrate, it still does not consider the SER problems experienced with ceramic substrates, as discussed herein before.